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Wednesday, May 13 • 11:40am - 11:55am
Signal Integrity Challenges for PCIe 5.0 OCP Topologies

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This presentation explores the signal integrity challenges of PCIe 5.0 and the corresponding OCP system design challenges, where the right balance must be found between PCB materials, connector types, and the use of signal conditioning devices for practical compute topologies: CPU-to-AIC with one/two connectors, JBOG accelerator module baseboard, etc. Each topology has multiple factors impacting SI—package, channel insertion/reflection loss, and crosstalk—requiring tradeoffs between physical channel length, interconnect solution, PCB design/material, etc. Through an objective analysis using open-source tools, the goal is to provide the audience with a step-by-step methodology to optimize their topology between low-loss PCB material, alternative connectors, signal retimers, or some combination thereof. Finally, to improve link uptime and maximize the potential of PCIe 5.0 throughput and latency, we explore the relationship between Lane BER and Link stability.

avatar for Casey Morrison

Casey Morrison

Head of Systems and Applications, Astera Labs
Casey Morrison leads Applications Engineering at Astera Labs and is responsible for product definition and customer design-in activities. With 12+ years of experience in high-speed interfaces for data center and wired/wireless communications systems, he has a passion for creating... Read More →
avatar for Pulkit Khandelwal

Pulkit Khandelwal

Technical Staff Member, Astera Labs
Pulkit Khandelwal (pulkit.khandelwal@asteralabs.com) leads Systems Engineering at Astera Labs, working on system applications, software/firmware development, and system validation. He has over 15 years of experience in data-center connectivity solutions, developing and deploying leading-edge PHYs and ASSPs for electrical and optical inte... Read More →

Wednesday May 13, 2020 11:40am - 11:55am
EW: Servers