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Tuesday, May 12 • 1:30pm - 2:30pm
Panel - Learnings from HBM Ecosystem for Optimal Die-to-Die Interconnect Solution

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High Bandwidth Memory (HBM) technology has matured over the last few years, and accelerator, GPU and network device provides are shipping products in volumes with the first and the second generations of the HBM memory, using Through Silicon Via (TSV) and 3D packaging.

With the growing interest in multi-chip packaging solutions, either for die disaggregation to split to improve yield and cost; or for the heterogeneous integration by bringing different functions into the same package for improved power, cost, and bandwidth. It is worth to take a closer look at what can be learned from the challenges that were overcome by the different parts of the HBM ecosystem before it was adopted. To find what can be learned, leveraged, and considered, as the ODSA sub-group works on the die-to-die solution specifications.

The panel will bring together experts with different backgrounds and experiences in HBM system design, packaging, test, tools, and end products to share their learnings, in order to address the die-to-die ecosystem needs for broader application and market needs.

Speakers
avatar for Rita Horner

Rita Horner

Product Marketing Manager, Sr. Staff, Synopsys
2.5D/3D IC Technologies with Multi-die integration
avatar for Anand Iyer

Anand Iyer

Director of Product Planning, Samsung Semiconductor, Samsung
CC

Calvin Cheung

Vice President, ASE Group
avatar for Lalitha Immaneni

Lalitha Immaneni

Intel Vice President, Technology Development Group; Director, Advanced Design and Technology Solutions Department, Intel
WG

Wilfred Gomes

Fellow, Intel


Tuesday May 12, 2020 1:30pm - 2:30pm PDT
EW: Open Domain-Specific Architecture