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Thursday, May 14 • 11:25am - 11:40am
PCIe Technology: Connecting OCP Architectures of the Future

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PCI Express® (PCIe®) architecture has enabled high performance in various systems and platforms for almost thirty years, and PCI-SIG® plans to continue this forward trajectory. While all PCIe specifications are backwards compatible, the evolution of PCI-SIG’s I/O technology is paving the way for future systems to make their mark on the high-performance computing (HPC) industry. PCIe specifications consistently deliver enhanced performance, unprecedented speeds and low latency. The PCIe 4.0 and PCIe 5.0 specifications—reaching 16 GT/s and 32GT/s transfer rates respectively—laid the groundwork for the PCIe 6.0 specification. PCIe 6.0 technology will continue the tradition of doubling previous data rates at 64 GT/s and rising to meet the needs of the most demanding workloads. The current PCI-SIG specification roadmap from the PCIe 4.0 specification to the PCIe 6.0 specification will continue to enable OCP architectures and platform designs for years to come.

In this session, attendees will:
• Examine case studies where PCIe specifications are being deployed in OCP architectures.
• Learn about the development status and exciting feature in the PCIe 6.0 specification, targeted for completion in 2021.
• Receive an update on official PCIe 4.0 specification compliance testing and current industry adoption.
• Gain insight into PCIe 5.0 specification traction and a status update on the development of the compliance tests.

Speakers
avatar for Al Yanes

Al Yanes

PCI-SIG Chairman and President, PCI-SIG
Al Yanes has served as president of the PCI-SIG since 2003 and chairman since 2006 and is a Distinguished Engineer for IBM in the Systems & Technology Division. He has 26 years of experience working with ASIC design in the I/O industry. Yanes holds 25 patents for PCI™ and other... Read More →


Thursday May 14, 2020 11:25am - 11:40am
EW: NIC 3.0 Interface/HPC